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Code
Activity
7f52c18a22
yosys
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passes
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Clifford Wolf
7f52c18a22
Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect
2014-02-08 19:13:19 +01:00
..
abc
Added support for "keep" attribute to abc pass
2014-02-08 14:25:29 +01:00
cmds
Added various new options to splice command
2014-02-08 16:37:18 +01:00
fsm
Fixes in fsm detect/extract for better detection of non-fsm circuits
2013-12-06 12:53:20 +01:00
hierarchy
Moved some passes to other source directories
2014-02-08 14:39:15 +01:00
memory
Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect
2014-02-08 19:13:19 +01:00
opt
Added opt -purge (frontend to opt_clean -purge)
2014-02-08 14:21:34 +01:00
proc
Tiny cleanup in proc_mux.cc
2014-01-03 16:54:59 +01:00
sat
Added generic RTLIL::SigSpec::parse_sel() with support for selection variables
2014-02-06 19:22:46 +01:00
techmap
Moved some passes to other source directories
2014-02-08 14:39:15 +01:00