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yosys/tests/arch/common
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whitequark 081d9318bc ecp5: add support for both 1364.1 and LSE RAM/ROM attributes. 
This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
  * LSE supports both `syn_ramstyle` and `syn_romstyle`.
  * Synplify only supports `syn_ramstyle`, with same values as LSE.
  * Synplify also supports `syn_rw_conflict_logic`, which is not
    documented as supported for LSE.

Limitations of the Yosys implementation:
  * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
    syntax to turn off insertion of transparency logic. There is
    currently no way to support multiple valued attributes in
    memory_bram. It is also not clear if that is a good idea, since
    it can cause sim/synth mismatches.
  * LSE/Synplify/1364.1 support block ROM inference from full case
    statements. Yosys does not currently perform this transformation.
  * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
    from the module to the inner memories. There is currently no way
    to do this in Yosys (attrmvcp only works on cells and wires).
2020-02-06 16:52:51 +00:00
..
memory_attributes Fixing compiler warning/issues. Moving test script to the correct place 2019-12-16 10:23:45 -06:00
add_sub.v Unify verilog style 2019-10-18 12:50:24 +02:00
adffs.v Unify verilog style 2019-10-18 12:50:24 +02:00
blockram.v ice40: add support for both 1364.1 and LSE RAM/ROM attributes. 2020-02-06 14:58:20 +00:00
blockrom.v ecp5: add support for both 1364.1 and LSE RAM/ROM attributes. 2020-02-06 16:52:51 +00:00
counter.v fixed error 2019-10-18 13:15:36 +02:00
dffs.v Unify verilog style 2019-10-18 12:50:24 +02:00
fsm.v Unify verilog style 2019-10-18 12:50:24 +02:00
latches.v Unify verilog style 2019-10-18 12:50:24 +02:00
logic.v Unify verilog style 2019-10-18 12:50:24 +02:00
lutram.v Rename memory tests to lutram, add more xilinx tests 2019-12-12 17:44:37 -08:00
mul.v Unify verilog style 2019-10-18 12:50:24 +02:00
mux.v Unify verilog style 2019-10-18 12:50:24 +02:00
shifter.v Unify verilog style 2019-10-18 12:50:24 +02:00
tribuf.v Unify verilog style 2019-10-18 12:50:24 +02:00