mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-14 21:08:47 +00:00
4 lines
66 B
Verilog
4 lines
66 B
Verilog
module test(input a, output x, y);
|
|
assign x = a, y = a;
|
|
endmodule
|