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https://github.com/YosysHQ/yosys
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dbc38d72cf
Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
13 lines
303 B
Verilog
13 lines
303 B
Verilog
module test1(a, b, c, d, e, f, y);
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input [19:0] a, b, c;
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input [15:0] d, e, f;
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output [41:0] y;
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assign y = a*b + c*d + e*f;
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endmodule
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module test2(a, b, c, d, e, f, y);
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input [19:0] a, b, c;
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input [15:0] d, e, f;
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output [41:0] y;
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assign y = a*b + (c*d + e*f);
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endmodule
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