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7e9e4c7afe
yosys
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frontends
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Akash Levy
7e9e4c7afe
Merge branch 'YosysHQ:main' into main
2025-06-23 02:30:24 -07:00
..
aiger
rtlil: represent Const strings as std::string
2024-10-14 06:28:12 +02:00
aiger2
aiger2: Clean debug print
2024-12-10 14:27:55 +01:00
ast
Merge pull request
#5163
from YosysHQ/emil/fix-single-bit-vector-leak
2025-06-04 17:00:54 +02:00
blif
Resolve reg naming to some extent
2024-12-17 12:11:39 -08:00
json
liberty
Liberty file caching with new
libcache
command
2025-04-03 13:39:35 +02:00
rpc
rtlil
read_rtlil: warn on assigns after switches in case rules
2024-11-21 22:41:13 +01:00
verific
Do not downgrade any warnings
2025-06-09 15:11:00 -07:00
verilog
verilog: fix parser "if" memory errors.
2025-06-22 23:57:42 -04:00