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33 lines
478 B
Text
33 lines
478 B
Text
read_verilog <<EOT
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module top(...);
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input [7:0] ra;
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input [7:0] rb;
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output gt;
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output sgt;
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output lt;
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output slt;
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output ge;
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output eq;
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output seq;
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output ne;
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assign gt = ra > rb;
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assign sgt = $signed(ra) > $signed(rb);
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assign lt = ra < rb;
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assign slt = $signed(ra) < $signed(rb);
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assign ge = ra >= rb;
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assign eq = ra == rb;
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assign seq = $signed(ra) == $signed(rb);
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assign ne = ra != rb;
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endmodule
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EOT
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proc
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equiv_opt -assert alumacc
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alumacc
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select -assert-count 1 t:$alu
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