Jannis Harder 5abaa59080 Merge pull request #3537 from jix/xprop ... New xprop pass		2023-01-11 16:26:04 +01:00
..
aiger
arch	fabulous: Allow adding extra custom prims and map rules	2022-11-17 13:34:58 +01:00
asicworld	Fix FIRRTL to Verilog process instance subfield assignment.	2019-02-25 16:18:13 -08:00
bind
blif	Adding check for BLIF names command input plane size.	2022-08-21 23:18:20 -05:00
bram	Fix the tests we just broke	2021-12-10 00:22:37 +01:00
errors
fsm
hana
liberty
lut
memfile
memlib	Add memory_libmap tests.	2022-05-18 17:32:56 +02:00
memories	Fix the tests we just broke	2021-12-10 00:22:37 +01:00
opt	simplemap: Map $xnor to $_XNOR_ cells	2022-11-29 19:06:45 +01:00
opt_share
proc	proc_rom: Add special handling of const-0 address bits.	2022-05-18 17:32:30 +02:00
realmath
rpc
sat	Proper example code	2022-03-14 15:39:11 +01:00
select
share
sim	Replace GNU specific invocation of basename(1) with the equivalent	2022-10-23 11:02:18 +13:00
simple	verilog: Support module-scoped task/function calls	2022-10-29 15:14:11 -04:00
simple_abc9
smv
sva	verific: Use new value change logic also for $stable of wide signals.	2022-05-11 13:05:27 +02:00
svinterfaces
svtypes	Support for packed multidimensional arrays within packed structs	2022-12-03 19:54:47 +01:00
techmap	Reenable existing equiv_opt tests	2022-10-07 16:04:51 +02:00
tools	support file locations containing spaces	2022-08-08 20:30:50 +02:00
unit
various	simplify: regression test for AST_CELLARRAY simplification issue	2022-12-07 18:41:55 +01:00
verilog	verilog: fix width/sign detection for functions	2022-05-30 16:45:39 -04:00
vloghtb
xprop	New xprop pass to encode 3-valued x-propagation using 2-valued logic	2022-11-30 19:01:28 +01:00
gen-tests-makefile.sh	support file locations containing spaces	2022-08-08 20:30:50 +02:00