Roland Coeurjoly 91e3773b51 Ensure signed constants are correctly parsed, represented, and exported in RTLIL. Add a test to check parsing and exporting		2024-08-21 14:28:42 +01:00
..
aiger	read_aiger: Fix incorrect read of binary Aiger without outputs	2024-04-29 14:06:58 +01:00
arch	inline all tests. Add switch to remove init values as PolarFire DFFs do not support init	2024-07-08 17:03:03 -04:00
asicworld
bind
blif
bram
cxxrtl	cxxxrtl: fix use of format specifiers in test	2024-06-11 07:22:39 +01:00
errors
fmt
fsm
hana
liberty	Extend liberty tests	2024-08-13 18:47:36 +02:00
lut
memfile
memlib
memories
opt	peepopt: avoid shift-amount underflow	2024-06-13 23:30:07 +02:00
opt_share
proc	proc_rom: test src attribute on memories	2024-07-29 10:13:45 +02:00
realmath
rpc
sat
select
share
sim
simple
simple_abc9
smv
sva
svinterfaces
svtypes
techmap	cellmatch: Rename the special design to $cellmatch	2024-05-03 16:42:41 +02:00
tools
unit
various	Ensure signed constants are correctly parsed, represented, and exported in RTLIL. Add a test to check parsing and exporting	2024-08-21 14:28:42 +01:00
verific
verilog
vloghtb
xprop
gen-tests-makefile.sh