mirror of
https://github.com/YosysHQ/yosys
synced 2026-01-05 02:28:51 +00:00
d1b767ea8b
Without OSER4_MEM, IDES4_MEM and DQS the synthesis of my Rocket Chip design for my Sipeed Tang FPGA fails. |
||
|---|---|---|
| .. | ||
| arith_map.v | ||
| brams.txt | ||
| brams_map.v | ||
| cells_map.v | ||
| cells_sim.v | ||
| cells_xtra.py | ||
| cells_xtra.v | ||
| lutrams.txt | ||
| lutrams_map.v | ||
| Makefile.inc | ||
| synth_gowin.cc | ||