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67 lines
1.6 KiB
Verilog
67 lines
1.6 KiB
Verilog
module constmuldivmod(input [7:0] A, input [5:0] mode, output reg [7:0] Y);
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always @* begin
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case (mode)
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0: Y = A / 8'd0;
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1: Y = A % 8'd0;
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2: Y = A * 8'd0;
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3: Y = A / 8'd1;
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4: Y = A % 8'd1;
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5: Y = A * 8'd1;
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6: Y = A / 8'd2;
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7: Y = A % 8'd2;
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8: Y = A * 8'd2;
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9: Y = A / 8'd4;
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10: Y = A % 8'd4;
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11: Y = A * 8'd4;
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12: Y = A / 8'd8;
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13: Y = A % 8'd8;
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14: Y = A * 8'd8;
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15: Y = $signed(A) / $signed(8'd0);
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16: Y = $signed(A) % $signed(8'd0);
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17: Y = $signed(A) * $signed(8'd0);
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18: Y = $signed(A) / $signed(8'd1);
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19: Y = $signed(A) % $signed(8'd1);
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20: Y = $signed(A) * $signed(8'd1);
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21: Y = $signed(A) / $signed(8'd2);
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22: Y = $signed(A) % $signed(8'd2);
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23: Y = $signed(A) * $signed(8'd2);
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24: Y = $signed(A) / $signed(8'd4);
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25: Y = $signed(A) % $signed(8'd4);
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26: Y = $signed(A) * $signed(8'd4);
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27: Y = $signed(A) / $signed(8'd8);
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28: Y = $signed(A) % $signed(8'd8);
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29: Y = $signed(A) * $signed(8'd8);
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30: Y = $signed(A) / $signed(-8'd0);
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31: Y = $signed(A) % $signed(-8'd0);
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32: Y = $signed(A) * $signed(-8'd0);
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33: Y = $signed(A) / $signed(-8'd1);
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34: Y = $signed(A) % $signed(-8'd1);
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35: Y = $signed(A) * $signed(-8'd1);
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36: Y = $signed(A) / $signed(-8'd2);
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37: Y = $signed(A) % $signed(-8'd2);
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38: Y = $signed(A) * $signed(-8'd2);
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39: Y = $signed(A) / $signed(-8'd4);
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40: Y = $signed(A) % $signed(-8'd4);
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41: Y = $signed(A) * $signed(-8'd4);
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42: Y = $signed(A) / $signed(-8'd8);
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43: Y = $signed(A) % $signed(-8'd8);
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44: Y = $signed(A) * $signed(-8'd8);
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default: Y = 8'd16 * A;
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endcase
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end
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endmodule
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