mirror of
https://github.com/YosysHQ/yosys
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218 lines
6.6 KiB
C++
218 lines
6.6 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef OPT_MERGE_COMMON_H
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#define OPT_MERGE_COMMON_H
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#include "kernel/yosys.h"
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#include "kernel/ffinit.h"
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#include "kernel/sigtools.h"
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#include "kernel/celltypes.h"
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#include "kernel/hashlib.h"
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#include <algorithm>
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#include <utility>
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YOSYS_NAMESPACE_BEGIN
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namespace OptMergeCommon {
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template <typename T, typename U>
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inline Hasher hash_pair(const T &t, const U &u) { return hash_ops<std::pair<T, U>>::hash(t, u); }
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// Shared cell hashing/comparison logic for opt_merge and opt_merge_inc.
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// When apply_sigmap is true, signals are run through assign_map before hashing
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// and comparison. When false, signals are used as-is (the caller is expected to
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// have pre-normalized them, e.g. via design->sigNormalize).
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struct CellHasher
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{
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const SigMap &assign_map;
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const FfInitVals &initvals;
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bool apply_sigmap;
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CellHasher(const SigMap &assign_map, const FfInitVals &initvals, bool apply_sigmap)
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: assign_map(assign_map), initvals(initvals), apply_sigmap(apply_sigmap) {}
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SigSpec map_sig(const SigSpec &sig) const {
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return apply_sigmap ? assign_map(sig) : sig;
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}
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static Hasher hash_pmux_in(const SigSpec& sig_s, const SigSpec& sig_b, Hasher h)
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{
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int s_width = GetSize(sig_s);
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int width = GetSize(sig_b) / s_width;
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hashlib::commutative_hash comm;
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for (int i = 0; i < s_width; i++)
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comm.eat(hash_pair(sig_s[i], sig_b.extract(i*width, width)));
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return comm.hash_into(h);
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}
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static void sort_pmux_conn(dict<RTLIL::IdString, RTLIL::SigSpec> &conn)
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{
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const SigSpec &sig_s = conn.at(ID::S);
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const SigSpec &sig_b = conn.at(ID::B);
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int s_width = GetSize(sig_s);
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int width = GetSize(sig_b) / s_width;
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std::vector<std::pair<SigBit, SigSpec>> sb_pairs;
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for (int i = 0; i < s_width; i++)
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sb_pairs.push_back(std::pair<SigBit, SigSpec>(sig_s[i], sig_b.extract(i*width, width)));
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std::sort(sb_pairs.begin(), sb_pairs.end());
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conn[ID::S] = SigSpec();
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conn[ID::B] = SigSpec();
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for (auto &it : sb_pairs) {
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conn[ID::S].append(it.first);
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conn[ID::B].append(it.second);
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}
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}
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Hasher hash_cell_inputs(const RTLIL::Cell *cell, Hasher h) const
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{
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// TODO: when implemented, use celltypes to match:
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// (builtin || stdcell) && (unary || binary) && symmetrical
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if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul),
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ID($logic_and), ID($logic_or), ID($_AND_), ID($_OR_), ID($_XOR_))) {
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hashlib::commutative_hash comm;
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comm.eat(map_sig(cell->getPort(ID::A)));
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comm.eat(map_sig(cell->getPort(ID::B)));
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h = comm.hash_into(h);
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} else if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
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SigSpec a = map_sig(cell->getPort(ID::A));
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a.sort();
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h = a.hash_into(h);
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} else if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) {
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SigSpec a = map_sig(cell->getPort(ID::A));
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a.sort_and_unify();
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h = a.hash_into(h);
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} else if (cell->type == ID($pmux)) {
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SigSpec sig_s = map_sig(cell->getPort(ID::S));
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SigSpec sig_b = map_sig(cell->getPort(ID::B));
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h = hash_pmux_in(sig_s, sig_b, h);
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h = map_sig(cell->getPort(ID::A)).hash_into(h);
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} else {
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hashlib::commutative_hash comm;
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for (const auto& [port, sig] : cell->connections()) {
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if (cell->output(port))
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continue;
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comm.eat(hash_pair(port, map_sig(sig)));
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}
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h = comm.hash_into(h);
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if (cell->is_builtin_ff())
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h = initvals(cell->getPort(ID::Q)).hash_into(h);
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}
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return h;
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}
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static Hasher hash_cell_parameters(const RTLIL::Cell *cell, Hasher h)
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{
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hashlib::commutative_hash comm;
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for (const auto& param : cell->parameters) {
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comm.eat(param);
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}
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return comm.hash_into(h);
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}
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Hasher hash_cell_function(const RTLIL::Cell *cell, Hasher h) const
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{
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h.eat(cell->type);
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h = hash_cell_inputs(cell, h);
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h = hash_cell_parameters(cell, h);
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return h;
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}
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bool compare_cell_parameters_and_connections(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2) const
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{
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if (cell1 == cell2) return true;
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if (cell1->type != cell2->type) return false;
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if (cell1->parameters != cell2->parameters)
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return false;
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if (cell1->connections_.size() != cell2->connections_.size())
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return false;
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for (const auto &it : cell1->connections_)
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if (!cell2->connections_.count(it.first))
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return false;
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decltype(RTLIL::Cell::connections_) conn1, conn2;
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conn1.reserve(cell1->connections_.size());
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conn2.reserve(cell1->connections_.size());
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for (const auto &it : cell1->connections_) {
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if (cell1->output(it.first)) {
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if (it.first == ID::Q && cell1->is_builtin_ff()) {
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// For the 'Q' output of state elements,
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// use the (* init *) attribute value
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conn1[it.first] = initvals(it.second);
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conn2[it.first] = initvals(cell2->getPort(it.first));
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}
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else {
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conn1[it.first] = RTLIL::SigSpec();
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conn2[it.first] = RTLIL::SigSpec();
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}
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}
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else {
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conn1[it.first] = map_sig(it.second);
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conn2[it.first] = map_sig(cell2->getPort(it.first));
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}
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}
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if (cell1->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul),
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ID($logic_and), ID($logic_or), ID($_AND_), ID($_OR_), ID($_XOR_))) {
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if (conn1.at(ID::A) < conn1.at(ID::B)) {
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std::swap(conn1[ID::A], conn1[ID::B]);
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}
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if (conn2.at(ID::A) < conn2.at(ID::B)) {
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std::swap(conn2[ID::A], conn2[ID::B]);
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}
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} else
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if (cell1->type.in(ID($reduce_xor), ID($reduce_xnor))) {
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conn1[ID::A].sort();
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conn2[ID::A].sort();
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} else
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if (cell1->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) {
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conn1[ID::A].sort_and_unify();
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conn2[ID::A].sort_and_unify();
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} else
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if (cell1->type == ID($pmux)) {
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sort_pmux_conn(conn1);
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sort_pmux_conn(conn2);
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}
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return conn1 == conn2;
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}
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bool has_dont_care_initval(const RTLIL::Cell *cell) const
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{
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if (!cell->is_builtin_ff())
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return false;
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return !initvals(cell->getPort(ID::Q)).is_fully_def();
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}
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};
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} // namespace OptMergeCommon
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YOSYS_NAMESPACE_END
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#endif
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