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yosys
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techlibs
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Andrew Zonenberg
cbdddc3af9
greenpak4_counters: Changed generation of primitive names so that the absorbed register's name is included
2017-06-24 14:54:07 -07:00
..
altera_intel
Squelch trailing whitespace
2017-04-12 15:11:09 +02:00
common
gowin
greenpak4
greenpak4_counters: Changed generation of primitive names so that the absorbed register's name is included
2017-06-24 14:54:07 -07:00
ice40
xilinx
.gitignore