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13 lines
389 B
Systemverilog
13 lines
389 B
Systemverilog
module sub_rom (input clk, input [3:0] addr, output reg [7:0] data);
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reg [7:0] mem [0:15];
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always @(posedge clk)
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data <= mem[addr];
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endmodule
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module top (input clk, input [3:0] addr, output [7:0] data, input [3:0] f_addr, input [7:0] f_data);
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sub_rom u_sub_rom (clk, addr, data);
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always @(posedge clk)
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assume(u_sub_rom.mem[f_addr] == f_data);
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endmodule
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