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yosys/techlibs/gatemate
History
gatecat 7c756c9959 gatemate: Add preliminary sim models for LUT tree structures 
Signed-off-by: gatecat <gatecat@ds0.me>
2022-06-27 10:09:48 +01:00
..
arith_map.v synth_gatemate: Initial implementation 2021-11-13 21:53:25 +01:00
brams.txt gatemate: Fix minor issues with memory_libmap (#3343) 2022-05-27 23:35:26 +02:00
brams_init_20.vh synth_gatemate: Initial implementation 2021-11-13 21:53:25 +01:00
brams_init_40.vh synth_gatemate: Revise block RAM read modes and initialization 2021-11-13 21:53:25 +01:00
brams_map.v gatemate: Fix minor issues with memory_libmap (#3343) 2022-05-27 23:35:26 +02:00
cells_bb.v synth_gatemate: Apply review remarks 2021-11-13 21:53:25 +01:00
cells_sim.v gatemate: Add preliminary sim models for LUT tree structures 2022-06-27 10:09:48 +01:00
lut_map.v synth_gatemate: Initial implementation 2021-11-13 21:53:25 +01:00
Makefile.inc synth_gatemate: Remove obsolete iob_map 2021-11-13 21:53:25 +01:00
mul_map.v synth_gatemate: Rename multiplier factor parameters 2021-11-13 21:53:25 +01:00
mux_map.v synth_gatemate: Initial implementation 2021-11-13 21:53:25 +01:00
reg_map.v synth_gatemate: Remove unsupported FF initialization 2021-11-13 21:53:25 +01:00
synth_gatemate.cc gatemate: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00