Jannis Harder 7203ba7bc1 Add bitwise $bweqx and $bwmux cells ... The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`) cells enable compact encoding and decoding of 3-valued logic signals using multiple 2-valued signals.		2022-11-30 18:24:35 +01:00
..
.gitignore
abc9_map.v
abc9_model.v
abc9_unmap.v
adff2dff.v
cellhelp.py
cells.lib
cmp2lcu.v
cmp2lut.v
dff2ff.v
gate2lut.v
gen_fine_ffs.py	Add $aldff and $aldffe: flip-flops with async load.	2021-10-02 18:12:52 +02:00
Makefile.inc	Add smtmap.v describing the smt2 backend's behavior for undef bits	2022-10-20 15:48:18 +02:00
mul2dsp.v	Fix files with CRLF line endings	2021-06-09 12:16:33 +02:00
pmux2mux.v
prep.cc
simcells.v	Add $aldff and $aldffe: flip-flops with async load.	2021-10-02 18:12:52 +02:00
simlib.v	Add bitwise $bweqx and $bwmux cells	2022-11-30 18:24:35 +01:00
smtmap.v	Add smtmap.v describing the smt2 backend's behavior for undef bits	2022-10-20 15:48:18 +02:00
synth.cc	Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}.	2022-06-02 23:16:12 +02:00
techmap.v	Add bitwise $bweqx and $bwmux cells	2022-11-30 18:24:35 +01:00