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yosys/techlibs
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Clifford Wolf bfcd46dbd3
Merge pull request #842 from litghost/merge_upstream 
Changes required for VPR place and route in synth_xilinx
2019-03-05 15:33:19 -08:00
..
achronix Reduce amount of trailing whitespace in code base 2019-02-28 14:58:11 -08:00
anlogic Reduce amount of trailing whitespace in code base 2019-02-28 14:58:11 -08:00
common Merge pull request #772 from whitequark/synth_lut 2019-01-02 15:44:57 +01:00
coolrunner2 Unify usage of noflatten among architectures 2019-01-04 11:37:25 +01:00
easic Fix typographical and grammatical errors and inconsistencies. 2019-01-02 13:12:17 +00:00
ecp5 ecp5: Demote conflicting FF init values to a warning 2019-03-04 11:26:20 +00:00
gowin Reduce amount of trailing whitespace in code base 2019-02-28 14:58:11 -08:00
greenpak4 techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module 2019-02-26 09:40:46 -08:00
ice40 ice40: use 2 bits for READ/WRITE MODE for SB_RAM map 2019-02-28 16:23:40 -08:00
intel Reduce amount of trailing whitespace in code base 2019-02-28 14:58:11 -08:00
sf2 Add SF2 IO buffer insertion 2019-01-17 14:38:37 +01:00
xilinx Merge pull request #842 from litghost/merge_upstream 2019-03-05 15:33:19 -08:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00