Martin Povišer b143e5678f cellmatch: Rename the special design to $cellmatch		2024-05-03 16:42:41 +02:00
..
aiger	read_aiger: Fix incorrect read of binary Aiger without outputs	2024-04-29 14:06:58 +01:00
arch	Add workflows and CODEOWNERS and fixed gitignore	2024-04-11 14:56:00 +02:00
asicworld
bind
blif
bram
cxxrtl	cxxrtl: Fix sdivmod	2024-03-30 07:56:11 +00:00
errors
fmt	cxxrtl: always lazily format print messages.	2024-01-19 18:55:23 +00:00
fsm
hana
liberty
lut
memfile
memlib	Move parameters to module declaration	2024-04-08 12:44:37 +02:00
memories	Move parameters to module declaration	2024-04-08 12:44:37 +02:00
opt	tests: Remove part of test involving combinational loops	2024-03-11 10:45:36 +01:00
opt_share
proc	proc_rom: don't assert on big actionless switch.	2024-02-18 01:33:28 +11:00
realmath
rpc
sat	Add support for $dimensions and $unpacked_dimensions	2024-02-11 11:26:52 -05:00
select
share
sim
simple	write_verilog: don't assign to a reg.	2024-04-03 13:06:45 +02:00
simple_abc9
smv
sva	tests/sva: Skip sva tests that use SBY until SBY is compatible again	2024-03-05 14:37:33 +01:00
svinterfaces
svtypes	fix test for verific	2024-02-12 09:19:58 +01:00
techmap	cellmatch: Rename the special design to $cellmatch	2024-05-03 16:42:41 +02:00
tools
unit	Changes in libs, passes and tests Makefiles. LDLIBS -> LIBS. LDFLAGS -> LINKFLAGS. CXX is clang++ or g++, not clang and gcc	2024-02-25 17:23:56 +01:00
various	add command that should not have any effect to hierarchy -generate test (this documents the current behavior, not sure if it is desired functionality)	2024-04-12 13:51:06 +02:00
verific	Add -nordff to test	2024-02-06 10:36:30 +01:00
verilog	write_verilog: don't assign to a reg.	2024-04-03 13:06:45 +02:00
vloghtb
xprop	tests: Comment on A[0]	2024-02-16 11:43:28 +01:00
gen-tests-makefile.sh	do not override existing shell variable	2024-02-12 12:58:13 +01:00