Marcelina Kościelnicka 9a4f420b4b Replace opt_rmdff with opt_dff.		2020-08-07 13:21:03 +02:00
..
tests	xilinx: Add simulation model for DSP48 (Virtex 4).	2020-01-29 01:40:00 +01:00
.gitignore
abc9_model.v	abc9_ops: add -prep_bypass for auto bypass boxes; refactor	2020-05-14 10:33:56 -07:00
arith_map.v	Remove EXPLICIT_CARRY logic.	2020-07-23 00:56:09 +02:00
brams_init.py
cells_map.v	xilinx: Use dfflegalize.	2020-07-09 18:54:23 +02:00
cells_sim.v	Remove EXPLICIT_CARRY logic.	2020-07-23 00:56:09 +02:00
cells_xtra.py
cells_xtra.v	xilinx: Mark IOBUFDS.IOB as external pad	2020-03-20 14:37:38 +01:00
ff_map.v	xilinx: Use dfflegalize.	2020-07-09 18:54:23 +02:00
lut4_lutrams.txt
lut6_lutrams.txt
lut_map.v	Add force_downto and force_upto wire attributes.	2020-05-19 01:42:40 +02:00
lutrams_map.v
Makefile.inc	xilinx: Use dfflegalize.	2020-07-09 18:54:23 +02:00
mux_map.v	Add force_downto and force_upto wire attributes.	2020-05-19 01:42:40 +02:00
synth_xilinx.cc	Replace opt_rmdff with opt_dff.	2020-08-07 13:21:03 +02:00
xc2v_brams.txt
xc2v_brams_map.v
xc3s_mult_map.v
xc3sa_brams.txt
xc3sda_brams.txt
xc3sda_dsp_map.v
xc4v_dsp_map.v
xc5v_dsp_map.v
xc6s_brams.txt	xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.	2020-02-07 01:00:29 +01:00
xc6s_brams_map.v
xc6s_dsp_map.v
xc7_brams_map.v
xc7_dsp_map.v
xc7_xcu_brams.txt
xcu_brams_map.v	xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.	2020-02-07 01:00:29 +01:00
xcu_dsp_map.v
xcup_urams.txt
xcup_urams_map.v
xilinx_dffopt.cc	Use C++11 final/override keywords.	2020-06-18 23:34:52 +00:00