mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-06 17:44:09 +00:00
Code Activity
yosys/techlibs/gowin
History
Lofty 7ae4041e20 ice40, ecp5, gowin: enable ABC9 by default
2023-11-13 15:28:13 +00:00
..
arith_map.v gowin: Fix X output of $alu techmap 2023-05-01 17:56:41 +02:00
brams.txt gowin: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
brams_map.v gowin: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
cells_map.v iopadmap: Add native support for negative-polarity output enable. 2021-11-09 15:40:16 +01:00
cells_sim.v gowin: fix abc9 attributes and specify blocks 2023-10-04 00:16:10 +01:00
cells_xtra.py gowin: Add all the primitives. 2023-04-22 17:10:53 +10:00
cells_xtra.v gowin: Add all the primitives. 2023-04-22 17:10:53 +10:00
lutrams.txt gowin: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
lutrams_map.v gowin: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
Makefile.inc gowin: Add all the primitives. 2023-04-22 17:10:53 +10:00
synth_gowin.cc ice40, ecp5, gowin: enable ABC9 by default 2023-11-13 15:28:13 +00:00