3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-26 02:25:35 +00:00
yosys/techlibs/ecp5
2023-11-13 15:28:13 +00:00
..
tests
arith_map.v
brams.txt
brams_map.v
cells_bb.v Add additional iopad_external_pin attributes 2023-03-20 09:17:22 +01:00
cells_ff.vh
cells_io.vh Add iopad_external_pin to some basic io primitives 2023-03-20 09:17:22 +01:00
cells_map.v
cells_sim.v ecp5: Remove TRELLIS_SLICE and add TRELLIS_COMB model 2023-04-06 10:18:48 +01:00
dsp_map.v
latches_map.v
lutrams.txt
lutrams_map.v
Makefile.inc ecp5_gsr -> lattice_gsr, change opt_lut_ins to accept lattice as tech 2023-08-22 10:50:11 +02:00
synth_ecp5.cc ice40, ecp5, gowin: enable ABC9 by default 2023-11-13 15:28:13 +00:00