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tests
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Improved xilinx "bram1" test
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2015-04-09 17:12:12 +02:00 |
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.gitignore
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Added support for initialized xilinx brams
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2015-04-06 17:07:10 +02:00 |
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arith_map.v
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Fixed trailing whitespaces
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2015-07-02 11:14:30 +02:00 |
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brams.txt
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Added read-enable to memory model
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2015-09-25 12:23:11 +02:00 |
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brams_bb.v
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Added Xilinx bram black-box modules
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2015-04-06 08:44:30 +02:00 |
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brams_init.py
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Squelch trailing whitespace, including meta-whitespace
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2018-03-11 16:03:41 +01:00 |
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brams_map.v
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Added read-enable to memory model
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2015-09-25 12:23:11 +02:00 |
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cells_map.v
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Fix cells_map for SRL
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2019-03-14 08:09:48 -07:00 |
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cells_sim.v
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Add SRL16 and SRL32 sim models
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2019-02-28 13:56:22 -08:00 |
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cells_xtra.sh
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Remove SRL16/32 from cells_xtra
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2019-02-28 13:56:45 -08:00 |
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cells_xtra.v
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Remove SRL16/32 from cells_xtra
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2019-02-28 13:56:45 -08:00 |
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drams.txt
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Added memory_bram "make_outreg" feature
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2015-04-09 16:08:54 +02:00 |
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drams_map.v
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Xilinx DRAMS: RAM64X1D, RAM128X1D
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2015-04-09 13:37:07 +02:00 |
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lut2lut.v
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Add techlibs/xilinx/lut2lut.v
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2017-07-10 12:09:05 +02:00 |
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Makefile.inc
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Add Xilinx RAM64X1D and RAM128X1D simulation models
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2018-03-07 17:31:48 +01:00 |
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synth_xilinx.cc
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Move shregmap until after first techmap
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2019-03-13 17:13:52 -07:00 |
