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38 lines
1.5 KiB
Verilog
38 lines
1.5 KiB
Verilog
(* techmap_celltype = /*"$shift*/ "$shiftx" *)
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module _80_shift_shiftx (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
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parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
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generate
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genvar i;
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localparam CLOG2_Y_WIDTH = $clog2(Y_WIDTH);
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if (B_WIDTH <= CLOG2_Y_WIDTH+1)
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wire _TECHMAP_FAIL_ = 1;
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// In order to perform this optimisation, this $shiftx must
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// only shift in units of Y_WIDTH, which we check by ensuring
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// that the appropriate LSBs of B are zero
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else if (_TECHMAP_CONSTMSK_B_[CLOG2_Y_WIDTH-1:0] == {CLOG2_Y_WIDTH{1'b1}} && _TECHMAP_CONSTVAL_B_[CLOG2_Y_WIDTH-1:0] != {CLOG2_Y_WIDTH{1'b0}})
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wire _TECHMAP_FAIL_ = 1;
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else begin
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// Halve the size of $shiftx by $mux-ing A according to
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// the LSB of B, after discarding the zeroed bits
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wire [(A_WIDTH+Y_WIDTH)/2-1:0] AA;
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for (i = 0; i < (A_WIDTH/Y_WIDTH); i=i+2)
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assign AA[(i/2)*Y_WIDTH +: Y_WIDTH] = B[CLOG2_Y_WIDTH] ? A[(i+1)*Y_WIDTH +: Y_WIDTH] : A[(i+0)*Y_WIDTH +: Y_WIDTH];
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$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+Y_WIDTH)/2'd2), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B({B[B_WIDTH-1:CLOG2_Y_WIDTH+1], {CLOG2_Y_WIDTH{1'b0}}}), .Y(Y));
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end
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endgenerate
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endmodule
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