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https://github.com/YosysHQ/yosys
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156 lines
3.1 KiB
Text
156 lines
3.1 KiB
Text
read_verilog abc9.v
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design -save read
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hierarchy -top abc9_test027
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proc
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design -save gold
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abc9 -lut 4
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check
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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design -load read
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hierarchy -top abc9_test028
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proc
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abc9 -lut 4
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select -assert-count 1 t:$lut r:LUT=2'b01 r:WIDTH=1 %i %i
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select -assert-count 1 t:unknown
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select -assert-none t:$lut t:unknown %% t: %D
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design -load read
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hierarchy -top abc9_test032
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proc
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clk2fflogic
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design -save gold
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abc9 -lut 4
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check
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -seq 10 -verify -prove-asserts -show-ports miter
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design -reset
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read_verilog -icells <<EOT
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module abc9_test036(input clk, d, output q);
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(* keep, init=1'b0 *) wire w;
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$_DFF_P_ ff(.C(clk), .D(d), .Q(w));
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assign q = w;
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endmodule
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EOT
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equiv_opt -assert abc9 -lut 4 -dff
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design -load postopt
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cd abc9_test036
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select -assert-count 1 t:$_DFF_P_
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select -assert-none t:* t:$_DFF_P_ %d
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design -reset
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read_verilog -icells -specify <<EOT
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(* abc9_lut=1, blackbox *)
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module LUT2(input [1:0] i, output o);
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parameter [3:0] mask = 0;
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assign o = i[0] ? (i[1] ? mask[3] : mask[2])
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: (i[1] ? mask[1] : mask[0]);
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specify
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(i *> o) = 1;
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endspecify
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endmodule
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module abc9_test037(input [1:0] i, output o);
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LUT2 #(.mask(4'b0)) lut (.i(i), .o(o));
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endmodule
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EOT
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abc9
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design -reset
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read_verilog -icells <<EOT
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module abc9_test038(input clk, output w, x, y, z);
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(* init=1'b1 *) wire w;
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$_DFF_N_ ff1(.C(clk), .D(1'b1), .Q(w));
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(* init=1'bx *) wire x;
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$_DFF_N_ ff2(.C(clk), .D(1'b0), .Q(x));
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(* init=1'b0 *) wire y;
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$_DFF_N_ ff3(.C(clk), .D(1'b0), .Q(y));
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(* init=1'b0 *) wire z;
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$_DFF_N_ ff4(.C(clk), .D(1'b1), .Q(z));
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endmodule
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EOT
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simplemap
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equiv_opt -assert abc9 -lut 4 -dff
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design -load postopt
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cd abc9_test038
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select -assert-count 3 t:$_DFF_N_
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select -assert-none c:ff1 c:ff2 c:ff4 %% c:* %D
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clean
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select -assert-count 2 a:init
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select -assert-count 1 w:w a:init %i
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select -assert-count 1 c:ff4 %co c:ff4 %d %a a:init %i
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# Check that non-dangling ABC9 black-boxes are preserved
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design -reset
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read_verilog -specify <<EOT
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(* abc9_box, blackbox *)
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module mux_with_param(input I0, I1, S, output O);
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parameter P = 0;
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specify
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(I0 => O) = P;
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(I1 => O) = P;
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(S => O) = P;
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endspecify
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endmodule
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module abc9_test039(output O);
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mux_with_param #(.P(1)) m (
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.I0(1'b1),
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.I1(1'b1),
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.O(O),
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.S(1'b0)
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);
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endmodule
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EOT
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abc9 -lut 4
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cd abc9_test039
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select -assert-count 1 t:mux_with_param
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# Check that dangling ABC9 black-boxes are swept away
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design -reset
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read_verilog -specify <<EOT
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(* abc9_box, blackbox *)
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module mux_with_param(input I0, I1, S, output O);
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parameter P = 0;
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specify
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(I0 => O) = P;
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(I1 => O) = P;
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(S => O) = P;
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endspecify
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endmodule
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module abc9_test040(output O);
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wire w;
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mux_with_param #(.P(1)) m (
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.I0(1'b1),
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.I1(1'b1),
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.O(w),
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.S(1'b0)
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);
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endmodule
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EOT
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abc9 -lut 4
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cd abc9_test040
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select -assert-count 0 t:mux_with_param
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