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af8e85b7d2
prjtrellis documentation shows that EBR clock inputs have optional inverters. The bram techmap outputs those parameters, and nextpnr consumes them. But for whatever reason, Diamond doesn't include those parameters in its blackbox models. This makes synth_lattice fail when targeting ECP5 with a design that maps block RAMs if you include any pass that needs cells_bb_ecp5.v's definitions. This change fixes up the ECP5 bram blackbox models at generation time, by adding the missing parameters back in. Signed-off-by: David Anderson <dave@natulte.net> |
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| .. | ||
| arith_map_ccu2c.v | ||
| arith_map_ccu2d.v | ||
| brams_8kc.txt | ||
| brams_16kd.txt | ||
| brams_map_8kc.v | ||
| brams_map_16kd.v | ||
| ccu2c_sim.vh | ||
| ccu2d_sim.vh | ||
| cells_bb_ecp5.v | ||
| cells_bb_xo2.v | ||
| cells_bb_xo3.v | ||
| cells_bb_xo3d.v | ||
| cells_ff.vh | ||
| cells_io.vh | ||
| cells_map.v | ||
| cells_sim_ecp5.v | ||
| cells_sim_xo2.v | ||
| cells_sim_xo3.v | ||
| cells_sim_xo3d.v | ||
| cells_xtra.py | ||
| common_sim.vh | ||
| dsp_map_18x18.v | ||
| latches_map.v | ||
| lattice_gsr.cc | ||
| lutrams.txt | ||
| lutrams_map.v | ||
| Makefile.inc | ||
| synth_lattice.cc | ||