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yosys/techlibs/xilinx
2020-01-23 19:02:27 -08:00
..
tests
.gitignore
abc9_map.v
abc9_model.v Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0 2020-01-23 19:02:27 -08:00
abc9_unmap.v
abc9_xc7.box
abc9_xc7.lut
abc9_xc7_nowide.lut
arith_map.v Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623 2020-01-17 12:02:46 -08:00
brams_init.py
cells_map.v
cells_sim.v
cells_xtra.py
cells_xtra.v
lut_map.v
lutrams.txt
lutrams_map.v
Makefile.inc
mux_map.v
synth_xilinx.cc Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623 2020-01-17 12:02:46 -08:00
xc3s_mult_map.v
xc3sda_dsp_map.v
xc4v_dsp_map.v
xc5v_dsp_map.v
xc6s_brams.txt
xc6s_brams_map.v
xc6s_dsp_map.v
xc6s_ff_map.v
xc7_brams_map.v
xc7_dsp_map.v
xc7_ff_map.v
xc7_xcu_brams.txt
xcu_brams_map.v
xcu_dsp_map.v
xcup_urams.txt
xcup_urams_map.v
xilinx_dffopt.cc