mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-07 09:55:20 +00:00
Code Activity
yosys/techlibs/anlogic
History
Icenowy Zheng 7854d5ba21 anlogic: fix dbits of Anlogic Eagle DRAM16X4 
The dbits of DRAM16X4 is wrong set to 2, which leads to waste of DRAM
bits.

Fix the dbits number in the RAM configuration.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-18 14:38:44 +08:00
..
anlogic_eqn.cc Initial support for Anlogic FPGA 2018-12-01 18:28:54 +01:00
arith_map.v Initial support for Anlogic FPGA 2018-12-01 18:28:54 +01:00
cells_map.v Initial support for Anlogic FPGA 2018-12-01 18:28:54 +01:00
cells_sim.v Initial support for Anlogic FPGA 2018-12-01 18:28:54 +01:00
drams.txt anlogic: fix dbits of Anlogic Eagle DRAM16X4 2018-12-18 14:38:44 +08:00
drams_map.v anlogic: add support for Eagle Distributed RAM 2018-12-17 23:20:40 +08:00
eagle_bb.v Revert "Leave only real black box cells" 2018-12-17 23:20:40 +08:00
Makefile.inc anlogic: add support for Eagle Distributed RAM 2018-12-17 23:20:40 +08:00
synth_anlogic.cc anlogic: add support for Eagle Distributed RAM 2018-12-17 23:20:40 +08:00