Marcelina Kościelnicka 4e70c30775 FfData: some refactoring. ... - FfData now keeps track of the module and underlying cell, if any (so calling emit on FfData created from a cell will replace the existing cell) - FfData implementation is split off to its own .cc file for faster compilation - the "flip FF data sense by inserting inverters in front and after" functionality that zinit uses is moved onto FfData class and beefed up to have dffsr support, to support more use cases		2021-10-07 04:24:06 +02:00
..
.gitignore
abc9_dff.ys	ast: Use better parameter serialization for paramod names.	2021-03-18 00:52:00 +01:00
add_sub.ys
adffs.ys
attributes_test.ys	xilinx: Fix attributes_test.ys	2020-10-24 23:52:37 +02:00
blockram.ys
bug1460.ys
bug1462.ys
bug1480.ys
bug1598.ys
bug1605.ys
counter.ys
dffs.ys
dsp_abc9.ys	xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)	2020-09-23 09:15:24 -07:00
dsp_cascade.ys
dsp_fastfir.ys
dsp_simd.ys
fsm.ys	FfData: some refactoring.	2021-10-07 04:24:06 +02:00
latches.ys	opt_expr: Remove -clkinv option, make it the default.	2020-07-31 00:08:15 +02:00
logic.ys
lutram.ys
macc.sh
macc.v
macc.ys
macc_tb.v
mul.ys
mul_unsigned.v
mul_unsigned.ys
mux.ys	xilinx_dffopt: Don't crash on missing IS_*_INVERTED.	2021-01-27 00:32:00 +01:00
mux_lut4.ys
nosrl.ys	xilinx: Fix srl regression.	2020-07-12 23:41:27 +02:00
opt_lut_ins.ys
pmgen_xilinx_srl.ys	satgen: Add support for dffe, sdff, sdffe, sdffce cells.	2020-07-24 03:19:21 +02:00
run-test.sh	tests: Centralize test collection and Makefile generation	2020-09-21 15:07:02 +02:00
shifter.ys
tribuf.sh
tribuf.ys
xilinx_dffopt.ys	xilinx_dffopt: Don't crash on missing IS_*_INVERTED.	2021-01-27 00:32:00 +01:00
xilinx_dffopt_blacklist.txt
xilinx_dsp.ys
xilinx_srl.v
xilinx_srl.ys