mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-25 10:05:33 +00:00
3 lines
82 B
Verilog
3 lines
82 B
Verilog
module test(input [1:0] in, output out);
|
|
assign out = ~(in[0] & in[1]);
|
|
endmodule
|