mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-03 21:09:12 +00:00
9 lines
370 B
Text
9 lines
370 B
Text
read_verilog ../common/shifter.v
|
|
hierarchy -top top
|
|
proc
|
|
flatten
|
|
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd top # Constrain all select calls below inside the top module
|
|
select -assert-count 8 t:SB_DFF
|
|
select -assert-none t:SB_DFF %% t:* %D
|