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yosys/techlibs/ice40
2020-04-03 05:51:40 +00:00
..
tests
.gitignore
abc9_hx.box
abc9_hx.lut
abc9_lp.box
abc9_lp.lut
abc9_model.v
abc9_u.box
abc9_u.lut
arith_map.v
brams.txt
brams_init.py
brams_map.v
cells_map.v
cells_sim.v
dsp_map.v
ice40_braminit.cc
ice40_ffinit.cc
ice40_ffssr.cc
ice40_opt.cc
latches_map.v
Makefile.inc
synth_ice40.cc ice40: do not map FFRAM if explicitly requested otherwise. 2020-04-03 05:51:40 +00:00