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https://github.com/YosysHQ/yosys
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7203ba7bc1
The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`) cells enable compact encoding and decoding of 3-valued logic signals using multiple 2-valued signals.
45 lines
1.9 KiB
C
45 lines
1.9 KiB
C
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef SIMPLEMAP_H
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#define SIMPLEMAP_H
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#include "kernel/yosys.h"
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YOSYS_NAMESPACE_BEGIN
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extern void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell);
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extern void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell);
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extern void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell);
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extern void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell);
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extern void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell);
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extern void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell);
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extern void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell);
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extern void simplemap_bwmux(RTLIL::Module *module, RTLIL::Cell *cell);
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extern void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell);
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extern void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell);
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extern void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell);
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extern void simplemap_ff(RTLIL::Module *module, RTLIL::Cell *cell);
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extern void simplemap(RTLIL::Module *module, RTLIL::Cell *cell);
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extern void simplemap_get_mappers(dict<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
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YOSYS_NAMESPACE_END
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#endif
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