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			64 lines
		
	
	
	
		
			1.8 KiB
		
	
	
	
		
			Bash
		
	
	
		
			Executable file
		
	
	
	
	
			
		
		
	
	
			64 lines
		
	
	
	
		
			1.8 KiB
		
	
	
	
		
			Bash
		
	
	
		
			Executable file
		
	
	
	
	
| #!/bin/bash
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| 
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| yosys_bin="/usr/local/synthesis/src/yosys/yosys"
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| hana_bin="/usr/local/synthesis/src/hana/bin/hana"
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| vl2mv_bin="/usr/local/synthesis/bin/vl2mv"
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| vis_bin="/usr/local/synthesis/bin/vis"
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| iverilog_bin="/usr/local/synthesis/bin/iverilog-0.8"
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| odin_bin="/usr/local/synthesis/src/vtr_release/ODIN_II/odin_II.exe"
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| abc_bin="/usr/local/synthesis/src/alanmi-abc-b5750272659f/abc"
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| edif2ngd="/opt/Xilinx/14.3/ISE_DS/ISE/bin/lin64/edif2ngd"
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| netgen="/opt/Xilinx/14.3/ISE_DS/ISE/bin/lin64/netgen"
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| 
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| all_modes="yosys hana vis icarus odin"
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| all_sources="always01 always02 always03 arrays01 forgen01 forgen02"
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| 
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| if [ "$*" == "ALL" ]; then
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| 	for mode in $all_modes; do
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| 		for src in $all_sources; do
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| 			echo "synth.sh $mode $src.v ${src}_${mode}.v"
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| 			( set -x; bash synth.sh $mode $src.v ${src}_${mode}.v || rm -f ${src}_${mode}.v; ) > ${src}_${mode}.log 2>&1
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| 		done
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| 	done
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| 	exit
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| fi
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| 
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| mode="$1"
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| source="$2"
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| output="$3"
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| prefix="${output%.v}"
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| 
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| help() {
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| 	echo "$0 ALL" >&2
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| 	echo "$0 {yosys|hana|vis|icarus|odin} <source-file> <output-file>" >&2
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| 	exit 1
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| }
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| 
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| if [ "$#" != 3 -o ! -f "$source" ]; then
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| 	help
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| fi
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| 
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| set -ex
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| 
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| case "$mode" in
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| 	yosys)
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| 		$yosys_bin -o $output -b "verilog -noattr" -p proc -p opt -p memory -p opt -p techmap -p opt $source ;;
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| 	hana)
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| 		$hana_bin -s $output $source ;;
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| 	vis)
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| 		$vl2mv_bin -o $prefix.mv $source
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| 		{ echo "read_blif_mv $prefix.mv"; echo "write_verilog $output"; } | $abc_bin ;;
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| 	icarus)
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| 		rm -f $prefix.ngo $prefix.v
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| 		$iverilog_bin -t fpga -o $prefix.edif $source
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| 		$edif2ngd $prefix.edif $prefix.ngo
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| 		$netgen -ofmt verilog $prefix.ngo $prefix.v
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| 		sed -re '/timescale/ s,^,//,;' -i $prefix.v ;;
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| 	odin)
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| 		$odin_bin -o $prefix.blif -V $source
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| 		sed -re 's,top\^,,g; s,clock,_clock,g;' -i $prefix.blif
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| 		{ echo "read_blif $prefix.blif"; echo "write_verilog $output"; } | $abc_bin ;;
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| 	*)
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| 		help
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| esac
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| 
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