mirror of
https://github.com/YosysHQ/yosys
synced 2026-07-15 03:35:40 +00:00
98656e284b
synth_gowin guarded the mul2dsp + dsp_map path to gw1n/gw2a, so GW5A multiplies expanded to LUTs. Add a gw5a branch mapping the GW5A's three multiplier widths: $__MUL27X18 (M0 27x18) for larger multiplies, $__MUL12X12 (M1 12x12) for <=12x12 (which pack two-per-block via M0+M1), and $__MUL27X36 (27x36) for wide (B>18) multiplies. The blocks are signed-only (no per-operand sign control), so DSP_SIGNEDONLY is mandatory without it a 32x16 -1*-1 mapping yields 0x08000001 instead of 1.
56 lines
666 B
CMake
56 lines
666 B
CMake
yosys_pass(synth_gowin
|
|
synth_gowin.cc
|
|
REQUIRES
|
|
abc
|
|
abc9
|
|
alumacc
|
|
autoname
|
|
blackbox
|
|
check
|
|
clean
|
|
deminout
|
|
dfflegalize
|
|
flatten
|
|
fsm
|
|
hierarchy
|
|
hilomap
|
|
iopadmap
|
|
memory
|
|
memory_libmap
|
|
memory_map
|
|
opt
|
|
opt_clean
|
|
opt_expr
|
|
opt_lut_ins
|
|
peepopt
|
|
proc
|
|
read_verilog
|
|
setundef
|
|
share
|
|
simplemap
|
|
sort
|
|
splitnets
|
|
stat
|
|
techmap
|
|
tribuf
|
|
wreduce
|
|
write_json
|
|
write_verilog
|
|
DATA_DIR
|
|
gowin
|
|
DATA_FILES
|
|
cells_map.v
|
|
cells_sim.v
|
|
cells_latch.v
|
|
cells_xtra_gw1n.v
|
|
cells_xtra_gw2a.v
|
|
cells_xtra_gw5a.v
|
|
arith_map.v
|
|
brams_map.v
|
|
brams_map_gw5a.v
|
|
brams.txt
|
|
lutrams_map.v
|
|
lutrams.txt
|
|
dsp_map.v
|
|
dsp_map_gw5a.v
|
|
)
|