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794cec0016
Chisel -> Firrtl -> Verilog -> Firrtl -> Verilog is successful for a simple rocket-chip design.
26 lines
395 B
Bash
26 lines
395 B
Bash
#!/bin/bash
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set -ex
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cd ../../
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make
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cd backends/firrtl
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../../yosys -q -p 'prep -nordff; write_firrtl test.fir' $1
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firrtl -i test.fir -o test_out.v -ll Info
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../../yosys -p "
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read_verilog $1
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rename Top gold
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read_verilog test_out.v
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rename Top gate
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prep
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memory_map
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miter -equiv -flatten gold gate miter
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hierarchy -top miter
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sat -verify -prove trigger 0 -set-init-zero -seq 10 miter
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"
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