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yosys/techlibs
History
Clifford Wolf bd10927f45 Progress in cell library documentation
2016-02-01 13:58:10 +01:00
..
common Progress in cell library documentation 2016-02-01 13:58:10 +01:00
greenpak4 Added nlutmap 2015-09-18 21:57:34 +02:00
ice40 Re-run ice40_opt in "synth_ice40 -abc2" 2015-12-22 12:19:11 +01:00
xilinx Added "abc -luts" option, Improved Xilinx logic mapping 2016-02-01 12:40:32 +01:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00