mirror of
https://github.com/YosysHQ/yosys
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166 lines
3 KiB
Text
166 lines
3 KiB
Text
read_verilog <<EOT
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module top(A, B, X, Y);
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input [7:0] A, B;
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output [7:0] X, Y;
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assign X = A + B;
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assign Y = A + B;
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endmodule
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EOT
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# Most basic case
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# Binary
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select -assert-count 2 t:$add
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equiv_opt -assert opt_merge
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design -load postopt
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module top(A, B, C, X, Y);
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input [7:0] A, B, C;
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output [7:0] X, Y;
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assign X = A + B;
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assign Y = A + C; // <- look here
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endmodule
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EOT
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# Reject on a different input
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select -assert-count 2 t:$add
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opt_merge
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select -assert-count 2 t:$add
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design -reset
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read_verilog <<EOT
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module top(A, X, Y);
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input [7:0] A;
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output X, Y;
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assign X = ^A;
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assign Y = ^A;
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endmodule
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EOT
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# Unary
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select -assert-count 2 t:$reduce_xor
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dump
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opt_merge
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select -assert-count 1 t:$reduce_xor
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design -reset
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read_verilog -icells <<EOT
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module top(A, B, X, Y);
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input [7:0] A, B;
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output X, Y;
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\$reduce_xor #(
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.A_SIGNED(32'd0),
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.A_WIDTH(32'd16),
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.Y_WIDTH(32'd1),
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) one (
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.A({A, B}), // <- look here
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.Y(X)
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);
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\$reduce_xor #(
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.A_SIGNED(32'd0),
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.A_WIDTH(32'd16),
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.Y_WIDTH(32'd1),
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) other (
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.A({B, A}), // <- look here
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.Y(Y)
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);
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endmodule
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EOT
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# Unary is sorted
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opt_expr
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select -assert-count 2 t:$reduce_xor
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equiv_opt -assert opt_merge
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design -load postopt
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select -assert-count 1 t:$reduce_xor
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design -reset
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read_verilog -icells <<EOT
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module top(A, B, X, Y);
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input [7:0] A, B;
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output X, Y;
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\$reduce_or #(
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.A_SIGNED(32'd0),
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.A_WIDTH(32'd24),
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.Y_WIDTH(32'd1),
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) one (
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.A({A, B, B}), // <- look here
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.Y(X)
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);
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\$reduce_or #(
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.A_SIGNED(32'd0),
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.A_WIDTH(32'd24),
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.Y_WIDTH(32'd1),
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) other (
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.A({A, A, B}), // <- look here
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.Y(Y)
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);
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endmodule
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EOT
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# Unary is unified when valid
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opt_expr
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select -assert-count 2 t:$reduce_or
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equiv_opt -assert opt_merge
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design -load postopt
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select -assert-count 1 t:$reduce_or
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design -reset
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read_verilog -icells <<EOT
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module top(A, B, X, Y);
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input [7:0] A, B;
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output X, Y;
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\$reduce_xor #(
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.A_SIGNED(32'd0),
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.A_WIDTH(32'd24),
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.Y_WIDTH(32'd1),
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) one (
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.A({A, B, B}), // <- look here
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.Y(X)
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);
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\$reduce_xor #(
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.A_SIGNED(32'd0),
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.A_WIDTH(32'd24),
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.Y_WIDTH(32'd1),
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) other (
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.A({A, A, B}), // <- look here
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.Y(Y)
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);
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endmodule
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EOT
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# Unary isn't unified when that would be invalid
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opt_expr
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select -assert-count 2 t:$reduce_xor
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equiv_opt -assert opt_merge
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design -load postopt
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select -assert-count 2 t:$reduce_xor
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# TODO pmux
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design -reset
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read_verilog <<EOT
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module top(A, B, X, Y);
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input [7:0] A, B;
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output X, Y;
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assign X = A > B;
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assign Y = A > B;
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endmodule
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EOT
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# Exercise the general case in hash_cell_inputs - accept
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opt_expr
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select -assert-count 2 t:$gt
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equiv_opt -assert opt_merge
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design -load postopt
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select -assert-count 1 t:$gt
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design -reset
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read_verilog <<EOT
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module top(A, B, C, X, Y);
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input [7:0] A, B, C;
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output X, Y;
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assign X = A > B;
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assign Y = A > C; // <- look here
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endmodule
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EOT
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# Exercise the general case in hash_cell_inputs - reject
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opt_expr
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select -assert-count 2 t:$gt
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opt_merge
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select -assert-count 2 t:$gt
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