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yosys/docs/source/using_yosys
History
Gary Wong 4ffd05af6f verilog: add support for SystemVerilog string literals. 
Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
2025-08-11 13:34:10 +02:00
..
more_scripting
synthesis
bugpoint.rst
index.rst
verilog.rst verilog: add support for SystemVerilog string literals. 2025-08-11 13:34:10 +02:00