mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-28 18:29:25 +00:00
50 lines
2 KiB
Text
50 lines
2 KiB
Text
### Q = D case.
|
|
|
|
read_verilog -icells <<EOT
|
|
|
|
module top(...);
|
|
|
|
input CLK;
|
|
input EN;
|
|
(* init = 24'h555555 *)
|
|
output [17:0] Q;
|
|
input SRST;
|
|
input ARST;
|
|
input [1:0] CLR;
|
|
input [1:0] SET;
|
|
|
|
$dff #(.CLK_POLARITY(1'b1), .WIDTH(2)) ff0 (.CLK(CLK), .D(Q[1:0]), .Q(Q[1:0]));
|
|
$dffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(2)) ff1 (.CLK(CLK), .EN(EN), .D(Q[3:2]), .Q(Q[3:2]));
|
|
$adff #(.CLK_POLARITY(1'b1), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff2 (.CLK(CLK), .ARST(ARST), .D(Q[5:4]), .Q(Q[5:4]));
|
|
$adffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff3 (.CLK(CLK), .EN(EN), .ARST(ARST), .D(Q[7:6]), .Q(Q[7:6]));
|
|
$sdff #(.CLK_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff4 (.CLK(CLK), .SRST(SRST), .D(Q[9:8]), .Q(Q[9:8]));
|
|
$sdffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff5 (.CLK(CLK), .EN(EN), .SRST(SRST), .D(Q[11:10]), .Q(Q[11:10]));
|
|
$sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff6 (.CLK(CLK), .EN(EN), .SRST(SRST), .D(Q[13:12]), .Q(Q[13:12]));
|
|
$dffsr #(.CLK_POLARITY(1'b1), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff7 (.CLK(CLK), .SET(SET), .CLR(CLR), .D(Q[15:14]), .Q(Q[15:14]));
|
|
$dffsre #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff8 (.CLK(CLK), .EN(EN), .SET(SET), .CLR(CLR), .D(Q[17:16]), .Q(Q[17:16]));
|
|
|
|
endmodule
|
|
|
|
EOT
|
|
|
|
design -save orig
|
|
|
|
equiv_opt -undef -assert -multiclock opt_dff -keepdc
|
|
|
|
design -load orig
|
|
opt_dff -keepdc
|
|
select -assert-count 1 t:$and
|
|
select -assert-count 3 t:$dffe
|
|
select -assert-count 2 t:$dlatch
|
|
select -assert-count 2 t:$sr
|
|
select -assert-none t:$and t:$dffe t:$dlatch t:$sr %% %n t:* %i
|
|
|
|
design -load orig
|
|
simplemap
|
|
opt_dff -keepdc
|
|
select -assert-count 2 t:$_AND_
|
|
select -assert-count 6 t:$_DFFE_??_
|
|
select -assert-count 4 t:$_DLATCH_?_
|
|
select -assert-count 4 t:$_SR_??_
|
|
select -assert-none t:$_AND_ t:$_DFFE_??_ t:$_DLATCH_?_ t:$_SR_??_ %% %n t:* %i
|
|
|