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72d65063c3
yosys
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frontends
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Martin Povišer
1ab7f29933
Start read_xaiger2 -sc_mapping
2024-09-18 16:42:56 +02:00
..
aiger
aiger2
Start read_xaiger2 -sc_mapping
2024-09-18 16:42:56 +02:00
ast
internal_stats: astnode (sizeof)
2024-09-11 11:34:20 +02:00
blif
json
fix handling of escaped chars in json backend and frontend
2022-02-18 17:13:09 +01:00
liberty
rpc
rtlil
Remove log
2024-08-21 14:28:42 +01:00
verific
Add left and right bound properties to wire. Add test. Fix printing
2024-09-10 12:52:42 +02:00
verilog