Clifford Wolf e9d73d2ee0 Indenting fixes in gowin sim cell lib		2016-11-08 18:54:00 +01:00
..
cells_map.v
cells_sim.v	Indenting fixes in gowin sim cell lib	2016-11-08 18:54:00 +01:00
Makefile.inc
synth_gowin.cc	Added hex constant support to write_verilog	2016-11-03 12:13:23 +01:00