Claire Xenia Wolf 72787f52fc Fixing old e-mail addresses and deadnames ... s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;		2021-06-08 00:39:36 +02:00
..
aiger	switch argument order to work with macOS getopt	2020-09-23 12:48:26 +02:00
arch	memory_bram: Reuse extract_rdff helper for make_outreg.	2021-05-25 22:42:03 +02:00
asicworld
blif	tests/blif: Add missing gitignore	2021-05-20 12:49:51 +02:00
bram	tests/bram: Do not generate write address collisions.	2021-03-08 16:53:03 +01:00
errors
fsm
hana
liberty
lut
memfile
memories
opt	memory_map: Improve start_offset handling.	2021-05-31 17:45:21 +02:00
opt_share
proc	proc_arst: Add special-casing of clock signal in conditionals.	2021-03-15 17:17:29 +01:00
realmath
rpc
sat	assertpmux: Fix crash on unused $pmux output.	2021-02-22 23:30:28 +01:00
select
share
simple	verilog: fix case expression sign and width handling	2021-05-25 16:16:46 -04:00
simple_abc9	abc9: fix SCC issues (#2694)	2021-03-29 22:01:57 -07:00
smv
sva
svinterfaces
svtypes	verilog: check entire user type stack for type definition	2021-03-21 19:35:13 -04:00
techmap	Add tests for some common techmap files.	2021-02-24 01:07:34 +01:00
tools	memory_dff: Remove now-useless write port handling.	2021-03-08 20:16:29 +01:00
unit
various	abc9: uniquify blackboxes like whiteboxes (#2695)	2021-03-29 22:02:06 -07:00
verilog	sv: support tasks and functions within packages	2021-06-01 13:17:41 -04:00
vloghtb	Fixing old e-mail addresses and deadnames	2021-06-08 00:39:36 +02:00
gen-tests-makefile.sh