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5 lines
207 B
Verilog
5 lines
207 B
Verilog
module test001(input [2:0] idx, input [31:0] data, output [3:0] slice_up, slice_down);
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wire [5:0] offset = idx << 2;
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assign slice_up = data[offset +: 4];
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assign slice_down = data[offset + 3 -: 4];
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endmodule
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