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https://github.com/YosysHQ/yosys
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643427d9c9
This commit introduces the negopt pass with pre/post optimization modes for handling negation patterns in arithmetic circuits. Pre-optimization patterns (expose for tree balancing): - manual2sub: (a + ~b) + 1 → a - b - sub2neg: a - b → a + (-b) - negexpand: -(a + b) → (-a) + (-b) [with output width fix] - negneg: -(-a) → a - negmux: -(s ? a : b) → s ? (-a) : (-b) Post-optimization patterns (cleanup/rebuild): - negrebuild: (-a) + (-b) → -(a + b) - muxneg: s ? (-a) : (-b) → -(s ? a : b) - neg2sub: a + (-b) → a - b All patterns use nusers() for fanout checking (standard Yosys style). Comprehensive test coverage with positive/negative cases and formal verification via equiv_opt.
60 lines
1.2 KiB
Text
60 lines
1.2 KiB
Text
log -header "Simple positive case"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, y);
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input wire signed [7:0] a;
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output wire signed [7:0] y;
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assign y = -(-a);
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -pre
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design -load postopt
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select -assert-none t:$neg
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design -reset
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log -pop
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log -header "With intermediate signal"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, y);
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input wire signed [7:0] a;
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output wire signed [7:0] y;
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wire signed [7:0] neg_a;
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assign neg_a = -a;
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assign y = -neg_a;
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -pre
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design -load postopt
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select -assert-none t:$neg
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design -reset
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log -pop
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log -header "Negative case: extra fanout on inner neg"
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log -push
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design -reset
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read_verilog <<EOF
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module top(a, y, z);
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input wire signed [7:0] a;
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output wire signed [7:0] y;
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output wire signed [7:0] z;
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(* keep *) wire signed [7:0] neg_a;
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assign neg_a = -a;
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assign y = -neg_a;
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assign z = neg_a;
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endmodule
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EOF
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proc; opt
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check -assert
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equiv_opt -assert negopt -pre
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design -load postopt
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# Should NOT transform due to extra fanout on inner neg output
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select -assert-count 2 t:$neg
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design -reset
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log -pop
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