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https://github.com/YosysHQ/yosys
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643427d9c9
This commit introduces the negopt pass with pre/post optimization modes for handling negation patterns in arithmetic circuits. Pre-optimization patterns (expose for tree balancing): - manual2sub: (a + ~b) + 1 → a - b - sub2neg: a - b → a + (-b) - negexpand: -(a + b) → (-a) + (-b) [with output width fix] - negneg: -(-a) → a - negmux: -(s ? a : b) → s ? (-a) : (-b) Post-optimization patterns (cleanup/rebuild): - negrebuild: (-a) + (-b) → -(a + b) - muxneg: s ? (-a) : (-b) → -(s ? a : b) - neg2sub: a + (-b) → a - b All patterns use nusers() for fanout checking (standard Yosys style). Comprehensive test coverage with positive/negative cases and formal verification via equiv_opt.
42 lines
1 KiB
Text
42 lines
1 KiB
Text
pattern sub2neg
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//
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// Authored by Abhinav Tondapu of Silimate, Inc. under ISC license.
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//
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// Convert subtraction to addition with negation
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//
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// a - b ===> a + (-b)
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//
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state <SigSpec> sub_a sub_b sub_y
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state <bool> a_signed b_signed
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match sub
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select sub->type == $sub
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filter !sub->getPort(\B).is_fully_const()
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set sub_a port(sub, \A)
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set sub_b port(sub, \B)
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set sub_y port(sub, \Y)
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set a_signed sub->getParam(\A_SIGNED).as_bool()
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set b_signed sub->getParam(\B_SIGNED).as_bool()
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endmatch
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code sub_a sub_b sub_y a_signed b_signed
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if (a_signed != b_signed)
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reject;
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{
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int width = GetSize(sub_y);
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SigSpec neg_y = module->addWire(NEW_ID, width);
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Cell *neg = module->addNeg(NEW_ID, sub_b, neg_y, b_signed);
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Cell *add = module->addAdd(NEW_ID, sub_a, neg_y, sub_y, a_signed);
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log("sub2neg pattern in %s: sub=%s -> neg=%s, add=%s\n",
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log_id(module), log_id(sub), log_id(neg), log_id(add));
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neg->fixup_parameters();
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add->fixup_parameters();
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autoremove(sub);
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did_something = true;
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}
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accept;
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endcode
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