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35 lines
843 B
Text
35 lines
843 B
Text
read_verilog -sv fuse_mac.sv
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design -save pristine
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# 18x18 MAC
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design -load pristine
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hierarchy -top mac;
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synth_nexus -family lifcl -top mac
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select -assert-count 1 t:MULTADDSUB18X18
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select -assert-count 0 t:CCU2
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# 18x18 pre-add MAC
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design -load pristine
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hierarchy -top madd_pre;
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synth_nexus -family lifcl -top madd_pre
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select -assert-count 1 t:MULTPREADD18X18
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# 4-lane 9x9 dot product
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design -load pristine
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hierarchy -top dot4;
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synth_nexus -family lifcl -top dot4
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select -assert-count 1 t:MULTADDSUB9X9WIDE
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# 24x24 MAC
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design -load pristine
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hierarchy -top neg_mac24;
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synth_nexus -family lifcl -top neg_mac24
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select -assert-count 0 t:MULTADDSUB18X18
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# mixed
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design -load pristine
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hierarchy -top neg_dot_mixed;
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synth_nexus -family lifcl -top neg_dot_mixed
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select -assert-count 0 t:MULTADDSUB9X9WIDE
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select -assert-count 2 t:MULTADDSUB18X18
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