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yosys/techlibs/common
2020-05-14 10:33:56 -07:00
..
.gitignore
abc9_map.v abc9: not enough to techmap_fail on (* init=1 *), hide them using $__ 2020-05-14 10:33:56 -07:00
abc9_model.v abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too 2020-05-14 10:33:56 -07:00
abc9_unmap.v abc9: not enough to techmap_fail on (* init=1 *), hide them using $__ 2020-05-14 10:33:56 -07:00
adff2dff.v
cellhelp.py
cells.lib
cmp2lcu.v techlibs/common: more robustness when *_WIDTH = 0 2020-05-05 08:01:27 -07:00
cmp2lut.v Cleanup +/cmp2lut.v 2020-04-03 14:28:22 -07:00
dff2ff.v
gate2lut.v Fix invalid verilog syntax 2020-03-14 14:33:44 +01:00
gen_fine_ffs.py Fix the truth table for $_SR_* cells. 2020-04-15 17:17:48 +02:00
Makefile.inc abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too 2020-05-14 10:33:56 -07:00
mul2dsp.v
pmux2mux.v
prep.cc
simcells.v Fix the truth table for $_SR_* cells. 2020-04-15 17:17:48 +02:00
simlib.v Fix the truth table for $_SR_* cells. 2020-04-15 17:17:48 +02:00
synth.cc synth: only techmap cmp2{lut,lcu} if -lut 2020-04-03 14:28:22 -07:00
techmap.v techlibs/common: more robustness when *_WIDTH = 0 2020-05-05 08:01:27 -07:00