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Code Activity
yosys/backends
History
whitequark 711df56ad0 write_cxxrtl: add support for $sr cell. 
Also, fix the semantics of SET/CLR inputs of the $dffsr cell, and
fix the scheduling of async FF cells to consider ARST/SET/CLR->Q
as a forward combinatorial arc.
2020-04-09 04:08:36 +00:00
..
aiger kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
blif kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
btor kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
cxxrtl write_cxxrtl: add support for $sr cell. 2020-04-09 04:08:36 +00:00
edif kernel: use more ID::* 2020-04-02 07:14:08 -07:00
firrtl kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
ilang Clean up pseudo-private member usage in backends/ilang/ilang_backend.cc. 2020-04-01 03:08:39 +00:00
intersynth Clean up pseudo-private member usage in backends/intersynth/intersynth.cc. 2020-04-01 06:32:09 +00:00
json json: Change compat mode to directly emit ints <= 32 bits 2020-02-09 01:01:18 -08:00
protobuf Add aiger and protobuf backends binary support 2019-09-28 09:51:48 +02:00
simplec kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
smt2 kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
smv kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
spice kernel: use more ID::* 2020-04-02 07:14:08 -07:00
table Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
verilog kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00