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50 lines
1.4 KiB
Text
50 lines
1.4 KiB
Text
# Testing edge cases where ports are signed/have different widths/shift amounts
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# greater than the size
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read_verilog <<EOT
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module top (
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input wire [3:0] in_u,
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input wire signed [3:0] in_s,
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output wire [7:0] shl_uu,
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output wire signed [7:0] shl_us,
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output wire [7:0] shl_su,
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output wire signed [7:0] shl_ss,
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output wire [7:0] shr_uu,
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output wire signed [7:0] shr_us,
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output wire [7:0] shr_su,
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output wire signed [7:0] shr_ss,
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output wire [7:0] sshl_uu,
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output wire signed [7:0] sshl_us,
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output wire [7:0] sshl_su,
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output wire signed [7:0] sshl_ss,
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output wire [7:0] sshr_uu,
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output wire signed [7:0] sshr_us,
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output wire [7:0] sshr_su,
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output wire signed [7:0] sshr_ss
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);
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assign shl_uu = in_u << 20;
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assign shl_us = in_u << 20;
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assign shl_su = in_s << 20;
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assign shl_ss = in_s << 20;
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assign shr_uu = in_u >> 20;
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assign shr_us = in_u >> 20;
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assign shr_su = in_s >> 20;
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assign shr_ss = in_s >> 20;
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assign sshl_uu = in_u <<< 20;
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assign sshl_us = in_u <<< 20;
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assign sshl_su = in_s <<< 20;
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assign sshl_ss = in_s <<< 20;
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assign sshr_uu = in_u >>> 20;
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assign sshr_us = in_u >>> 20;
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assign sshr_su = in_s >>> 20;
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assign sshr_ss = in_s >>> 20;
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endmodule
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EOT
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equiv_opt opt_expr
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design -load postopt
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select -assert-none t:$shl
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select -assert-none t:$shr
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select -assert-none t:$sshl
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select -assert-none t:$sshr
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