Lofty 77327b2544 sta: very crude static timing analysis pass ... Co-authored-by: Eddie Hung <eddie@fpgeh.com>		2021-11-25 17:20:27 +01:00
..
cmds	sta: very crude static timing analysis pass	2021-11-25 17:20:27 +01:00
equiv
fsm
hierarchy	verilog: use derived module info to elaborate cell connections	2021-10-25 18:25:50 -07:00
memory
opt	gowin: widelut support (#3042)	2021-11-06 16:09:30 +01:00
pmgen	Make it work on all	2021-11-05 10:51:58 +01:00
proc	proc_dff: Emit $aldff.	2021-10-27 14:14:24 +02:00
sat
techmap	sta: very crude static timing analysis pass	2021-11-25 17:20:27 +01:00
tests