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yosys/tests/verific
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Akash Levy 9cc82c7044 Revert clocking.ys
2025-02-13 20:32:17 -08:00
..
.gitignore
blackbox.ys.DISABLED
blackbox_empty.ys.DISABLED
blackbox_ql.ys.DISABLED
bounds.sv
bounds.vhd
bounds.ys.DISABLED
case.sv
case.ys
clocking.ys
enum_values.sv
enum_values.ys
memory_semantics.ys.DISABLED
range_case.sv
range_case.ys
README.md
rom_case.ys.DISABLED
run-test.sh
setenv.flist
setenv.ys

README.md

Verific Test Cases

Disabled

  • bounds: relies on using Verific's VHDL frontend
  • memory_semantics: relies on initial values being retained, which we do not want
  • rom_case: relies on using Verific's VHDL frontend
  • blackbox*: we need different behavior for parametrized blackboxes